High data reliability, high speed of memory access, and reduced chip size are features that are demanded from semiconductor memory.
In recent years, there has been an effort to increase access speed while reducing power consumption for semiconductor devices. As part of that effort to increase access speed, it may be desirable to include input receiver circuits having faster operation in input buffers for receiving address signals, command signals and clock signals. Simultaneously, it may be desirable to accommodate a wide range of input signals at the input receiver circuits to meet recent semiconductor devices (e.g., low-power double data rate synchronous DRAM). For example, Low Power Double Data Rate 4 (LPDDR4) specification (JESD209-4) specifies that an data input reference voltage (VREF) operating point range from 10% to 42% of a power supply voltage for data input (VDD). Along these lines, an input receiver circuit including differential amplifiers have been developed. For example, a data latch type input buffer has been used as an input buffer for memory devices (e.g., LPDDR4). A data latch type input (DQ) buffer in a memory device amplifies a data signal and latches the data signal by amplifying a voltage difference between the data input signal and the VREF when a clock signal CLK is at a logic high level, and initializes each node in the DQ buffer by precharging each node when the clock signal CLK is at a logic low level. The DQ input buffer performs a sequence of amplification and latch operation responsive to a signal input and a precharge operation in turn during each clock cycle. Source nodes of input transistors may receive a power supply voltage VDD and gate nodes of the input transistors coupled to input nodes (IN+ node and IN− node) may receive a data input signal DQ and the reference voltage VREF, respectively while performing the sequence of amplification and latch operation. However, the input transistors may not be driven fast enough due to a smaller VGS of the input transistors M1 and M2, if a voltage of the data input signal DQ and the reference voltage VREF become higher (e.g., VREF=42%*VDD).
FIG. 1 is a circuit diagram of a conventional data input buffer circuit. The conventional data input buffer circuit includes a first amplifier including transistors M1, M2, M3, M4, M5 and M6. A transistor M0 is a switch of the first amplifier. A data input signal DQ is provided to an IN+ node coupled to a gate of the transistor M1. The reference voltage VREF is provided to an IN− node coupled to a gate of the transistor M2. A sequence of amplification and latch operation are executed, when an inverted clock signal CLKB is at a logic low level that activates the transistor M0 and deactivates transistors M7-M10. The power supply voltage VDD is provided to nodes, (node 1 and node 2) through transistors M1 and 1192, and voltages of the nodes (node 1 and node 2) are increased from a precharge level VSS responsive to the inverted clock signal CLKB is at the logic low level, depending on the data input signal DQ. Thus, a voltage difference Vdiff between the nodes (node 1 and node 2) may be caused based on a difference between a voltage of the input data input signal DQ and the reference voltage VREF. Because the power supply voltage VDD is provided to nodes, (node 1 and node 2), voltages at an OUT− node and an OUT+ node may be increased from the precharge level VSS through transistors M3 and M4 respectively, when the voltage difference Vdiff exceeds a threshold voltage VTh of the transistor M3 or a threshold voltage VTh of the transistor M4. Due to voltages of the node 2 and the node 2 that are increased up to approximately the power supply voltage VDD, the first amplifier latches a voltage difference between the OUT− node and the OUT+ node of the first amplifier, and a logic high level signal (VDD) is provided to one of the OUT− node and the OUT+ node and a logic low level signal (VSS) is provided to the other of the OUT− node and the OUT+ node. In a precharge operation, when the inverted clock signal CLKB is at a logic high level, the nodes node 1, node 2, OUT− and OUT+ are precharged by precharge transistors M7, M8, M9 and M10 to the a logic low level signal (VSS). An increase of the voltage of the node 1 above the threshold VTh of the transistor M3 drives capacitors (not shown) related to the transistor M1 and capacitors coupled to the OUT− node, (e.g., capacitors at gates of the transistors M4 and MG, a channel capacitor of the transistor M3 and a drain capacitor of the transistor M5), and a total capacitance of these capacitors is remarkably large. Similarly, a total capacitance of capacitors related to the transistor M2 is large. Accordingly, a time to increase voltages of the nodes (node 1 and node 2) around the power supply voltage VDD and to complete the sequence of amplification and latch operation to increase voltages at an OUT− node and an OUT+ node is longer when the data input signal DQ and the reference voltage VREF are higher, and the sequence of amplification and latch operation may not be completed by a precharge operation in the data input buffer circuit.
FIG. 2 is a circuit diagram of a conventional data input buffer circuit. The conventional data input buffer circuit includes a first amplifier and a second amplifier. The first amplifier includes transistors M1 and M2. The second amplifier includes transistors M12, M13, M14, M15, M16 and M17. A transistor M0 is a switch of the first amplifier and a transistor M11 is a switch of the second amplifier. A sequence of amplification and latch operation are executed, when a clock signal CLK is at a logic high level and an inverted clock signal CLKB is at a logic low level. Responsive to a difference in voltage increase speeds between nodes (node 1 and node 2) at gates of transistors M12 and M13, the second amplifier latches a data signal and a signal at a logic low level (VSS) is provided to one of an OUT− node and an OUT+ node, and a precharge level (VDD) is provided to the other outputted at the other of OUT− and OUT+. In the precharge operation, node 1 and node 2 are set to a logic low level (VSS), and the OUT− node and the OUT+ node are precharged to the power supply voltage VDD responsive to the transistors M12 and M13 receiving the logic low level signal of the node 1 and node 2 at gates and coupling the power supply voltage VDD to the OUT− node and the OUT+ node. Since each of the transistors M1 and M2 includes a MOS capacitor having a capacitance smaller than a MOS capacitor in each of the transistors M1 and M2 of FIG. 1, voltages of node 1 and node 2 are increased faster than the voltages of node 1 and node 2 of FIG. 1. However, the second amplifier may complete a latch operation before a voltage difference between node 1 and node 2 is to be generated, if a voltage of the data input signal DQ and the reference voltage VREF become higher (e.g., VREF=42%*VDD). Thus, an activation of the second amplifier needs to be delayed. On the other hand, if the voltage of the data input signal DQ and the reference voltage VREF become lower, the voltages of node 1 and node 2 are increased too fast due to larger VGS of the transistors M1 and M2, and the voltages of node 1 and node 2 reach to approximately the power supply voltage VDD and the voltage difference disappears before the second amplifier completes the amplification, which causes a data latching failure.